B.Sc. in EE, SW Eng or computer science from university. At least one year’s experience in Verification. Object/Aspect Oriented programming at a very good level- SystemVerilog /”e”/C++ Scripting language- Perl /tcl / csh / python - anadvantage. VLSI design- Verilog / VHDL - an advantage. VMM verificationexperience – an advantage.
